1. Field of the Invention
This invention relates to communications interfaces, and more particularly to a locktoggle command to request either the start or the end of a lock condition.
2. Description of the Related Art
In computer systems, especially computer systems including multiple processors that may access memory or I/O (input/output) spaces concurrently, some mechanism is needed to assure that atomic accesses to memory are not interrupted by another system device. For example, a first system device may want to read a location in memory and then write a new value to that same memory location, as in the case of a memory-based variable. Some mechanism is needed to xe2x80x9clockxe2x80x9d the system so that a second system device cannot also read and/or write the same memory location before the first system device has finished with the memory location operations. In general, a locked operation may be defined as a sequence of one or more read cycles followed by one or more write cycles from a given device to a given memory location or range. No other device has access to at least the given memory location during the sequence comprising the locked operation.
In x86 processors, the locking functionality is provided for certain instructions that use a LOCK prefix. Certain other instructions implicitly specify that memory reads and writes be locked. It is noted that locked operations may also include page table updates and interrupt acknowledge cycles, as well. In the x86 hardware, locking has traditionally been implemented through a LOCK# pin on the x86 processor. A processor performing a lock. operation asserts the LOCK# pin during the sequence of reads and writes comprising the locked operation. Since x86 processors have generally been designed into computer systems in which processor access to memory is provided through a single shared processor bus, the LOCK# pin assertion may be used to dedicate the shared bus resource to the locking processor. As other processors sharing the bus resource are inhibited from accessing the shared bus while the shared bus is locked, other processors cannot interrupt the atomic sequence of reads and writes.
Unfortunately, shared bus systems suffer from several drawbacks. For example, since there are multiple devices attached to the shared bus, the bus is typically operated at a relatively low frequency. The multiple attachments present a high capacitive load to a device driving a signal on the bus, and the multiple attach points present a relatively complicated transmission line model for high frequencies. Accordingly, the frequency remains low, and bandwidth available on the shared bus is similarly relatively low. The low bandwidth presents a barrier to attaching additional devices to the shared bus, as performance may be limited by available bandwidth.
Another disadvantage of the shared bus system is a lack of scalability to larger numbers of devices. As mentioned above, the amount of bandwidth is fixed (and may decrease if adding additional devices reduces the operable frequency of the bus). Once the bandwidth requirements of the devices attached to the bus (either directly or indirectly) exceeds the available bandwidth of the bus, devices will frequently be stalled when attempting access to the bus. Overall performance of the computer system may thus be decreased.
Since x86 processors have continued to increase in operating frequency and overall performance, the shared computer bus computer system model is becoming a performance limitation. A method for providing lock functionality in a non-shared bus system is therefore desired.
The problems outlined above are in large part solved by a system and method for using a toggle command for setting and releasing a lock, i.e. a locktoggle. In an exemplary computer system, one or more processors are each coupled to a bus bridge through separate high speed connections, which in one embodiment each include a pair of unidirectional address buses with respective source-synchronous clock lines and a bi-directional data bus with attendant source-synchronous clock lines. The locktoggle command is used to transmit both a lock request and an unlock request from a processor to a system coherency point, e.g. the bus bridge. The system coherency point acknowledges when the lock has been established or released. While the lock is active, other processors are inhibited from accessing at least the memory locations for which the lock was initiated. Locks are thus established at the system coherency point, which may advantageously allow for locking functionality in a non-shared bus system. The use of the locktoggle command may also advantageously allow for the use of a single command code point, leaving other points available for other uses.
Broadly speaking, a processor is contemplated, comprising a decode unit, a load/store unit, and a system interface controller. The decode unit is coupled to receive and decode a first one or more instructions that specify a lock. The decode unit is configured to generate a lock indication in response to the first one or more instructions. The load/store unit is coupled to receive the lock indication and the first one or more instructions from the decode unit. The load/store unit is configured to select the first one or more instructions for execution and to transmit a first request for a locktoggle command in response thereto. The system interface controller is coupled between the load/store unit and a bus. The system interface controller is configured to receive the first request for the locktoggle command from the load/store unit and to issue the first locktoggle command in response to receiving the request for the first locktoggle command. The load/store unit is further configured to transmit a second request for the locktoggle command in response to executing the first one or more instructions. The system interface controller is further configured to receive the second request for the locktoggle command from the load/store unit and to issue the second locktoggle command in response to receiving the second request for the locktoggle command.
A bridge for coupling one or more processors into a computer system is also contemplated. Broadly speaking, the bridge comprises a first input port coupled to receive a plurality of commands from a first one of the one or more processors, a first processor queue coupled to the first. input port, a lock register configured to store a lock condition, and control logic coupled to the first input queue and the lock register. The first input port is configured to transfer the plurality of commands from the first one of said one or more processors to the first processor queue. The first processor queue is configured to store the plurality of commands from the first one of the one or more processors. The plurality of commands from the first one of the one or more processors includes a locktoggle command. The control logic is configured to remove the plurality of commands from the first one of the one or more processors from the first processor queue. In response to removing the locktoggle command from the first processor queue, the control logic is configured to check the lock condition. The control logic is further configured to set the lock condition to indicate a lock for the first one of the one or more processors if the lock condition indicates a lack of lock. The control logic is further configured to set the lock condition to indicate the lack of lock if the lock condition indicates the lock.
A computer system is also contemplated. Broadly speaking, the computer system comprises one or more processors and a bridge coupled to the one or more processors. The bridge is configured to execute commands received from the one or more processors. Each of the one or more processors is configured to transmit a locktoggle command to the bridge to request that a lock condition be set to indicate a lock. The bridge is configured in response to receiving the locktoggle command from a first one of the one or more processors to check the lock condition. The control logic is further configured to set the lock condition to indicate the lock for the first one of the one or more processors if the lock condition indicates a lack of lock and to set the lock condition to indicate the lack of lock if the lock condition indicates the lock.
A method for operating a computer system including one or more processors and a system device is also contemplated. Broadly speaking, the method comprises issuing a first locktoggle command from a first processor of the one or more processors to the system device. The method further checks an indication of a lock condition in the system device in response to the first locktoggle command. The method further comprises setting the lock condition to indicate a lock by the first processor in response to checking the indication of the lock condition and determining that the lock condition indicates a lack of lock. The method also sets the lock condition to indicate the lack of lock in response to checking the indication of the lock condition and determining that the lock condition indicates lock.